1. Field of the Invention
The present invention relates to a method and apparatus for the efficient operation of a programmable controller (hereinafter referred to as a "PC") under the programmed instructions of a processing unit (herein a "CPU") and, in particular, the generation of an execution file, the execution of such file and the display of information indicative of the instructions and processing carried out by the CPU.
2. Description of the Background Art
Programs for operating a PC which exercises sequence control ("sequence programs") are written with several different types of instructions, including (i) "basic instructions" for performing bit processing corresponding to relay operation, (ii) "function instructions" for implementing more complex operation and control, and (iii) other instructions.
These sequence programs are generally programmed as ladder diagrams in a ladder language, comprising the basic instructions, function instructions, and other instructions, with reference to a flowchart.
Programmable controllers for performing fast bit processing for sequence control were disclosed in Japanese Patent Publication No. 38902 of 1987 and Japanese Patent Publication No. 304302 of 1988. In these conventional controllers, however, their function instructions have a low processing speed. This is because the function instructions are developed in a macro-program and are software-processed. Furthermore, these PC instructions are subject to ladder display functions which result in low execution speeds.
The "ladder language" referred to herein is a programming language in which input/output signals are written with symbols, such as electrical circuit symbols that conventionally represent relay contacts and relay coils. Also, for example, a processing function such as "count up" is written with an instruction symbol (mnemonic) such as INC (Increment). The ladder language is suitable for user programming in an interactive form.
It should be noted that there are other languages in which such electrical circuit symbols are written with mnemonic instruction symbols, such as LD (Load) and LDI (Load Inverse), and processing functions are written similarly with mnemonic instruction symbols. These languages are adequate for programming employing a PC which does not have a graphic function and programming using a computer.
In a conventional processing operation, a sequence program written in a ladder language is converted into a "machine language" corresponding to the various instructions and is stored in a memory in the PC via a program input device. A CPU (central processing unit) is operative to read and execute each instruction step of the stored sequence program cyclically in sequence, thereby carrying out desired sequence control.
If it is desired to display the sequence program as a ladder diagram on a display device, such as a CRT (Cathode Ray Tube), the PC memory contains a converter program. The converter program sequentially reads the sequence program instructions written in the machine language from the memory, decodes them, outputs the ladder language corresponding to the machine language to the CRT, and displays it as a ladder diagram.
Such control will now be described with reference to FIG. 8 to FIG. 12.
FIG. 8 is a PC configuration diagram known in the art, wherein a CPU 1 is connected to a memory 2, that stores programs and information required for the PC to exercise control, via the direct connection of an address bus 3 for specifying memory addresses and the indirect connection of a data bus 4 for transferring data at the specified addresses of the memory. A bit operation instruction detector 5 is for detecting basic instructions which perform bit processing. A no-operation (NOP) instruction generator circuit 6 will return a response to the CPU 1 at the time of a basic instruction, the response NOP being via a sub-data bus 7 for inputting the output of the no-operation instruction generator circuit 6 to a selector. A bit operation processor 9 is for performing the processing of bit operation instructions as basic instructions and also connects to the CPU 1 via a system data bus 10, which also transfers data to and from the CPU 1 and each circuit and device. One such device is a digital input/output circuit 11 for inputting various signals and outputting processing results in response to sequence processing, which also is connected to a switch input 12, a relay contact input from a relay circuit 13, a lamp 14, and a relay coil 15. Another device connected to bus 10 is a keyboard 16 and a CRT acting as interfaces between the PC and an operator. A further device connected to bus 10 is a floppy disk drive 17 for storing various programs and data.
In the memory 2, there are a variety of sub-storage areas, including a control table 201 for storing data required for program processing of the PC, and an interrupt processing program 202 for carrying out processing, e.g., immediate reading of coordinate data initiated by an interrupt signal or the like in a measuring operation, etc.
First a control transition will be described in accordance with FIG. 9 by taking as an example the PC which is used with a numerical control (hereinafter referred to as "NC") apparatus. NC processing includes control which reads a machining program and moves a tool along a tool path specified by the machining program at a specified speed. The machining program consists of linear interpolation and circular interpolation commands for specifying the tool path and the tool compensation commands for compensating for tool dimensions, etc. Processing time depends on the combination of these commands, e.g., when only the linear interpolation command is used, the processing time is short, and when the circular interpolation and tool compensation commands are combined, the processing time is long. The processing time changes according to the control status and operation complexity.
In a NC processing environment, the PC is being operated under control of a main program "d". The control transition is started up by a reference interrupt signal "a". In response to the servicing of the interrupt, the PC first executes a program to be processed periodically in a cycle of the reference interrupt signal that was generated, i.e., a high-speed processing program "c". When this high-speed processing program ends, the PC carries out NC processing "e" (e.g., linear and circular interpolations, pulse distribution processing and the like) and thereafter resumes a main processing program "d", i.e., a sequence program, from where it had been stopped during the previous execution. After that, on occurrence of another reference interrupt signal "a", the PC stops the execution of the main processing "d" and executes the programs in a sequence of high-speed processing "c", NC processing "e" and the rest of main processing "d".
When an interrupt signial is input, the PC stops the currently executed NC processing program and runs an interrupt processing program "b", for example, for storing a memory content at a prodetermined address . When the a execution of this interrupt program ends, the PC resumes the previously stopped NC processing program from where it left off. unlike the high-speed processing "c" which runs the whole program every time it is started, the main processing "d", executes the program cyclically. At the end of each cycle of operation, it sometimes is stopped by another program of higher priorlty.
The operation of the PC will now be described with reference to the configuration in FIG. 8. The CPU 1 is started at predeter mined intervals (for instance, 7 msec) by a starting circuits not shown, which generates the reference interrupt signal, and specifies an address of the memory 2 via the address bus 3 to read the content of the memory 2 at the predetermined address.
At this time, the high-speed processing program 203 is first executed from its beginning. Such program could provide, for example, a position count control, etc., for a turret and an ATC (automatic tool changer) magazine of a machine tool (not shown) which are mounted with tools.
When the CPU 1 specifies the memory address via the address bus 3, the memory content at the corresponding address is read and output to the data bus 4. The memory content output onto data bus 4 is decoded by the bit operation instruction detector 5, which determines whether the content is a "basic instruction" for executing a bit operation or a "function instruction" for carrying out high-level operation processing.
When it has been determined that the content read is a basic instruction, a bit operation instruction detection signal is output to the NOP generator circuit 6, which then outputs a NOP code representing a no-operation instruction onto the sub-data bus 7. At this time, the bit operation instruction detection signal is also output from the bit operation instruction detector 5 to the selector 8, which then outputs onto the system data bus 10 the NOP code representing the no-operation instruction output onto the sub-data bus 7.
Further, the bit operation instruction detection signal is also output from the bit operation instruction detector 5 to the bit operation processor 9, which then performs processing, e.g., turns on/off a predetermined bit at the memory address specified by the basic instruction of the PC. In the meantime, the CPU 1 executes the no-operation instruction output onto the system data bus 10 and progresses to a step next to the basic instruction of the PC.
For a function instruction of the PC, the bit operation instruction processor 5 does not output the bit operation instruction detection signal. Hence, the selector 8 outputs the data content, which has been read from the memory 2 and output onto the data bus 4, intact onto the system data bus 10, and the CPU 1 executes programmed control by analyzing the data from selector 8.
The sequence program is thus executed in sequence, predetermined processing is carried out according to the states of various input signals, such as the switch input 12 and relay contact input 13, the lamp(s) 14 are lit and extinguished, and the relay coil(s) 15 are controlled on/off.
As a result, the spindle motor and other components of the machine tool controlled by the NC apparatus containing the PC are switched on/off, and forward/reverse rotation, coolant, etc., are controlled on/off.
Program conversion and control sequences in the conventional PC will now be described.
FIG. 10 illustrates a program conversion sequence in the conventional PC, FIG. 12 shows a flowchart for a data move instruction program and corresponding specific instruction examples, and FIG. 11 shows a program structure and a control sequence in the known PC. It should be noted that in FIG. 11, a memory width is represented and described in 32 bits for convenience.
Referring to FIG. 10, 211a indicates ladder language input data, which is input to a working RAM 211' by an operator from the keyboard/CRT 16 in FIG. 8 in accordance with a ladder diagram shown below 211a. The working RAM comprises a RAM (Random Access Memory), allowing data to be rewritten optionally.
A ladder language/intermediate language conversion program 207 reads a ladder program from the ladder language input data 211a sequentially, converts each step of the ladder program into an intermediate language separated into each component element with reference to a ladder language/intermediate language conversion table 208a, and generates an intermediate language file 211b in the working RAM 211'.
As a preliminary matter, the PC instructions that are referenced in the intermediate language file in FIG. 10 comprise the following:
"LD"--In the PC instructions, LD (short for "Load") is the basic instruction which reads the content of the specified bit on memory to the specified register and executes the subsequently commanded instruction if the result is "1". PA1 "LDI"--LDI (short for "Load Inverse") is the basic instruction which, like LD, reads the content of the specified bit on memory to the specified register. It is different from LD in that the inversed content of the bit is read. Therefore, "LDI M100" indicates that the inversed content of the bit defined as M100 on memory is read to the register.
For example, "LD M123" indicates that the content of the bit defined as M123 on memory is read to the register. Hence, if the content of the bit defined as M123 is "1 ", "1" is read to the register. Reversely, if the content of the bit is "0", "0" is read to the register. If the result is "1", the "MOVE D200 D100" instruction commanded subsequently is executed. Conversely, if the result is "0", "MOVE D200 D100" is skipped and the "LDI M100" instruction commanded subsequently to "MOVE D200 D100" is executed.
In the example, if the content of the bit defined as M100 is "1", "0" is read to the register. By contrast, if the content of the bit is "0", "1" is read to the register. If the result is "1", the "INC D800" instruction commanded subsequently is executed. In contrast, if the result is "0", "INC D800" is skipped and the instruction (not shown) commanded subsequently to "INC D800" is executed.
"MOVE"--is the function instruction of the PC which transfers the content of an identified register to another identified register.
For example, "MOVE D200 D100" is the function instruction of the PC which transfers the content of the data register defined as D200 to the data register defined as D100."MOVE D200 D100" is implemented by the macroprogram as shown in FIG. 12.
"INC"--"INC" is the function instruction which has the function of adding (incrementing) 1 to the content of an identified data register.
For example, "INC D800" instructs the addition of 1 to the content of the data register defined as D800.
After the intermediate language file is generated, compiler 209 converts each element of the intermediate language file 211b into a machine language with reference to an intermediate language/machine language conversion table 210a, and inputs the results to a main processing program 204 in the memory 2 as an "execution file" comprising CPU instructions. The ladder program thus written in a ladder language is converted into a CPU 1 executable machine language file and is stored into the main processing program 204 in the memory 2.
The machine language, which is represented by 0's and 1's , is the only representation that a computer can recognize but is not suitable for easy understanding by man. In the present description, therefore, the machine language is divided on a four-bit basis and the four bits are represented in hexadecimal (HEXA).
In FIG. 10, a macroprogram file 206 contains programs stored in the PC, which have been written separately in advance as shown in FIG. 12 in a C language for achieving function instructions, translated into the machine language by the compiler, and stored in the memory 2 as existing programs.
The head addresses of these programs are stored in a jump table 205 and a transition to a desired program can be made by referring to the jump table 205.
FIG. 12 shows a macroprogram designed to accomplish a MOVE function of the PC which transfers data stored in a memory area having a first-specified data number to a memory area having a next-specified data number.
Unless otherwise noted, instructions employed in describing the following program are written in an assembler language for use with the CPU 1 and the assembler language is translated by the compiler into the machine language, i.e., instructions with which the CPU 1 operates. In the present specification, the PC instruction and intermediate language are described in UPPERCASE and the assembler language in lowercase for ease of identification.
When a corresponding macroprogram is called, the content of a stack pointer "sp", which stores a memory 2 address and is located next to the address where a function instruction used to call such macroprogram is stored, is first read to a register a0 in step 1.
In step 2, it is checked whether a condition for executing the MOVE instruction of the PC, i.e., relay contact information, is 1 or not.
The position of this flag to be checked is fixed by the PC hardware and is herein bit 0 of an address specified by FLAG.
If the result of this check is 0, the execution branches to step 6. If the check result is 1, the execution advances to step 3.
In step 3, a register needed for the processing is cleared.
In step 4, the data number of a transfer source specified attendantly on the MOVE function instruction of the PC is first fetched and the head address of a data table is then read. The head address of the data table is then added to the data number, thereby finding a memory address of the data number of the transfer source. Finally, data stored at the resultant memory address is read to a register d0.
As in step 4, the data number of a transfer destination is fetched and the head address of the data table is added to the data number in step 5, thereby obtaining a memory address of the data number, of the transfer destination. Finally, data stored in the register d0 is written to the memory address found.
In step 6, 8 (one byte) is added to match the stack pointer with an address where a next-valid PC instruction is stored.
FIG. 11 shows a program structure and a control sequence in the conventional PC, and combines the execution file and jump table in the machine language created by the program conversion illustrated in FIG. 10 and the machine language file, such as the macroprogram, which achieves the MOVE function, etc., illustrated in FIG. 12.
In the structure shown in FIG. 11, high-speed processing is executed by the reference interrupt signal, NC processing is then performed, and sequence processing is thereafter resumed from where the main processing program had been stopped. The cycle is repeated to carry out control by the control apparatus combining the NC and PC.
If, during the execution of the main processing program, the CPU 1 specifies, for example, a memory 2 address where a PC function instruction of MOVE D200 D100 (actually, this instruction written in the machine language and stored in the memory is three-step information, beginning with a code having a jump function, which is represented 4EAD02BO in HEXA) is stored, the code stored at the corresponding address is read and output onto the data bus 4. Since this code is not a basic instruction, the bit operation instruction detector 5 controls the selector 8 so that the code output onto the data bus 4 is output onto the system data bus 10.
Accordingly, the code 4EAD02BO is read to the CPU I, which further judges that the code is a function instruction from the 16-bit code of 4EAD. The CPU 1 refers to information on the MOVE instruction stored starting at an address offset by 02B0 output to the 16 least significant bits of the code, beginning at the head address specified in the jump table. The head address is an absolute address in the memory 2 where the macro program for the targeted MOVE function and the attributes of the macroprogram are stored.
By transferring control from the instruction to the absolute address where the macroprogram for the targeted MOVE function is stored and executing an instruction group as shown in FIG. 11 in sequence, starting at that absolute address, the CPU 1 transmits data from a transfer source data number designated in the sequence program to a designated transfer destination data number.
When the macroprogram has been executed to the end, the CPU 1 specified a memory 2 address indicated by the stack pointer updated by the postprocessing of the macroprogram, i.e., a memory 2 address where an instruction next to the just executed MOVE function instruction of the PC in the sequence program is stored, and continues the decoding and execution of instructions.
Meanwhile, when the sequence program is diplayed, a machine language/ladder information conversion program (converter) 212a is employed to read and analyze the first instruction information of the main processing program 204. These instruction include information on relationships between the machine language and ladder language and information on the lengths of corresponding instructions. Reference to a machine language/ladder language conversion table 213a according to corresponding information provides a corresponding ladder language and a memory address where a next-read instruction exists. For instance, the code "4EAD02B0" reveals that it is JSR $02B0, i.e., an instruction of three steps long, "MOVE, data transfer source number, data transfer destination number." The data transfer source number and data transfer destination number are stored in the second and third steps. According to this information, predetermined graphic information may be added to the format of the MOV instruction and the result output to the CRT.
Therefore, by causing the converter 212a to read instructions from the beginning of the sequence program stored in the main processing program 204 in sequence and to convert the instructions into the ladder language in accordance with the machine language/ladder language conversion table 213a, the machine language written in the main processing program area 204 can be displayed on the display device as a ladder diagram.
The conventional PC designed as described above has certain disadvantages:
To execute a single "function instruction", a procedure for accomplishing a predetermined function must be preprogrammed and a large number of processing steps in a macroprogram stored in the memory 2 must be executed. In addition, a step for extracting the storage address of the macroprogram is needed before the program is reached. Hence, a high-level sequence program employing many function instructions will be executed longer and respond slower.
Also, if the CPU instructions of "move (a1), d0" in the step 4 and "move d0, (a1)" in the step 5 as shown in FIG. 12 are combined or integrated to generate a move instruction which directly designates memory addresses, processing speed increases but these instructions must be manually programmed in the assembler language. Also, these instructions do not include information required for restoration to the original ladder language, disallowing ladder display.